The present invention is generally directed to a system and method for timing generation in successive approximation register (SAR) analog-to-digital conversion. More specifically, the subject system and method provide for selective generation of a timing profile used in actuating an SAR analog-to-digital converter ADC.
SAR ADC architecture has long been favored in many applications requiring high speed, low power consumption, and suitably high conversion resolution. For conversion to an n-bit digital word, an SAR ADC generally operates to sample an analog input signal voltage then carry out a binary search for the corresponding quantized level to be coded via the n-hit word. The binary search is carried out over each of the bit positions in the n-bit word, with a comparator comparing the sampled input signal voltage against a succession of voltage reference levels. This comparison is thereby made for each successive “state” of the n-bit word as it is updated bit-by-bit in a successive approximation register.
The voltage reference levels for the states are successively provided according to an SAR state machine. The levels are set for each state by an internal reference digital-to-analog converter (DAC) relative to a supply voltage VIF. For each state, the SAR state machine prescribes the voltage reference level according to the quantization value then defined by the n-bit digital word.
An SAR ADC processing cycle thus includes a sampling phase followed by a conversion phase, during which a series of bit determinations are successively made. This cycle is repeated for subsequent samples of the input analog signal.
With ongoing advances in device technologies, there is ever increasing demand for greater speed in such processing. For deep submicron semiconductor technologies, for instance, it is a significant challenge to preserve ample timing for full and proper execution of SAR ADC processing cycles.
Attempts have been made in the art to optimize the timing generated for SAR ADC processing. In one self-timed approach, the SAR ADC detects when the comparator ompletes a comparison for bit determination in the current state, then automatically initiates the next state for the determination of the following bit. While such approaches do improve timing efficiencies, they do not ensure ample allocation of the available SAR processing cycle time between the sampling and conversion phases (successive bit determinations) of each cycle.
What is more, the internal reference DAC of an SAR ADC invariably exhibits a non-trivial settling time between bit determinations. This settling time varies with the prevailing conversion rate, process corner, and such environmental factors as temperature. The known attempts to optimize timing fail to ensure adequate time for settling of the internal reference DAC between successive bit determinations. There is therefore a need for a system and method which overcomes such deficiencies, and optimally generates the timing required for full and proper SAR ADC processing.